Design Verification Engineers – SOC (System 0n Chip)
Job Description
Position: Design Verification Engineers – SOC (System 0n Chip)
Location: Bangalore
Experience: 2 – 8 yrs
Qualification: B.E / B.Tech / M.E / M.Tech / MCA / M.Sc
Key Skills: Specman, System Verilog, Vera, GLS
ROLES AND RESPONSIBILITIES:-
Implementation of medium complex test bench components (monitors, checkers)from the given design document. Competent enough to design simple test benches for unit level verification.
Worked for at least two medium complexity HDL based verification projects. Competent enough to setup code coverage environment. Gate level simulations and debug.
Expert in PERL scripting. Competent enough to design and implement HDL based verification environment for small and medium complexity designs. Competent enough to design random verification environment using HDL. Gate level verification environment set up.
Expert in design and implement the HDL environment for the high complexity designs, Selection of re-usable verification IPs, "Understanding of verification and coverage plans” - able to extract test scenarios from the plan.
Good Understanding of HVL concepts. Able to code test scenario using existing HVL test bench with the given test plan. Knowledge of HVL test bench components, debugging HVL environment. Understanding of functional coverage metric and identification of additional scenarios.
Understanding of functional coverage metric and identification of additional scenarios.
Able to build HVL test benches for simple designs. Competent enough to implement medium complex HVL test bench modules like monitors, checker, BFMs etc., from the given verification plan. Able to implement basic functional coverage modules based on coverage plan.
Salary:Not Disclosed by Recruiter
Industry:Telecom, ISP
Functional Area:Engineering Design, R&D
Role Category:Engineering Design
Role:Senior Design Engineer
Keyskills:ASIC, System Verilog, Specman, SOC, vlsi, , verification, , vmm, asic - verification, OVM, UVM
Desired Candidate Profile
Education:(UG - B.Tech/B.E.) AND (PG - Any PG Course - Any Specialization, Post Graduation Not Required)
Please refer to the Job description above
Position: Design Verification Engineers – SOC (System 0n Chip)
Location: Bangalore
Experience: 2 – 8 yrs
Qualification: B.E / B.Tech / M.E / M.Tech / MCA / M.Sc
Key Skills: Specman, System Verilog, Vera, GLS
ROLES AND RESPONSIBILITIES:-
Implementation of medium complex test bench components (monitors, checkers)from the given design document. Competent enough to design simple test benches for unit level verification.
Worked for at least two medium complexity HDL based verification projects. Competent enough to setup code coverage environment. Gate level simulations and debug.
Expert in PERL scripting. Competent enough to design and implement HDL based verification environment for small and medium complexity designs. Competent enough to design random verification environment using HDL. Gate level verification environment set up.
Expert in design and implement the HDL environment for the high complexity designs, Selection of re-usable verification IPs, "Understanding of verification and coverage plans” - able to extract test scenarios from the plan.
Good Understanding of HVL concepts. Able to code test scenario using existing HVL test bench with the given test plan. Knowledge of HVL test bench components, debugging HVL environment. Understanding of functional coverage metric and identification of additional scenarios.
Understanding of functional coverage metric and identification of additional scenarios.
Able to build HVL test benches for simple designs. Competent enough to implement medium complex HVL test bench modules like monitors, checker, BFMs etc., from the given verification plan. Able to implement basic functional coverage modules based on coverage plan.
Salary:Not Disclosed by Recruiter
Industry:Telecom, ISP
Functional Area:Engineering Design, R&D
Role Category:Engineering Design
Role:Senior Design Engineer
Keyskills:ASIC, System Verilog, Specman, SOC, vlsi, , verification, , vmm, asic - verification, OVM, UVM
Desired Candidate Profile
Education:(UG - B.Tech/B.E.) AND (PG - Any PG Course - Any Specialization, Post Graduation Not Required)
Please refer to the Job description above
Company Profile
Sasken Communication Technologies Ltd
Sasken Communication Technologies Ltd
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