Sr. Signal Integrity Engineer

Performing static timing and signal integrity analysis of parallel (common clock, source-synchronous) interfaces

- Generating and verifying PCB layout rules

- Working directly with ASIC and PCB design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability

- Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs

- Design and analysis of multi-gigabit serial links

- Electromagnetic modeling of complex 3-dimensional structures

- Modeling and analyzing power delivery networks

- Performing physical measurements to collect data for design validation and simulation correlations

- Making recommendations on processes to improve capabilities and increase efficiency


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