Experience:
3 - 8 Years
Location:
Dallas ,
United States (U.S)
United States (U.S)
Education:
UG - B.Tech/B.E. - Electronics/TelecomunicationPG - M.Tech - Electronics/Telecomunication
Industry Type:
Semiconductors/ Electronics
Role:
Team Lead/Tech Lead
Functional Area:
Embedded/EDA /VLSI/ASIC/Chip Design
Posted Date:
19 Sep
Job Description
Location: Dallas (USA)
Experience: 3-8 years
Experience: 3-8 years
1. Position: ASIC Verification Engineer
Necessary Skills:
Necessary Skills:
-Strong Specman experience
-Strong debugging skills
-Experience writing testbenches, test plans, test generation, etc. -Good skills in VHDL or Verilog
Additional Skills (nice to have):
-Strong debugging skills
-Experience writing testbenches, test plans, test generation, etc. -Good skills in VHDL or Verilog
Additional Skills (nice to have):
-Good Perl, TCL, Shell scripting experience for ASIC Verification purposes
-Good programming skills in C Verification experience in chip level memory sub-systems like cache controller, memory controller or similar DDR memory
-Excellent written and oral communication skills
-Good programming skills in C Verification experience in chip level memory sub-systems like cache controller, memory controller or similar DDR memory
-Excellent written and oral communication skills
2. Position: VLSI Physical Design Engineer
PD Tasks:
-Integration/DIX checks/IR analysis
-BE checks + DRC/LVS clean up
-Physical Design closure + STA for PHY macro
-Physical Design closure in Cadence EDI flow
-Integration/DIX checks/IR analysis
-BE checks + DRC/LVS clean up
-Physical Design closure + STA for PHY macro
-Physical Design closure in Cadence EDI flow
3. Position: VLSI DFT Engineer
DFT Tasks:
-PBIST TDL generation and QC
-ATPG / TFT TDL generation and QC – Cadence
-PBIST TDL generation and QC
-ATPG / TFT TDL generation and QC – Cadence
Keywords: ASIC Verification, SOC Design, RTL, SOC Physical Design, DFT,
Desired Candidate Profile
1. Position: ASIC Verification Engineer
Necessary Skills:
-Strong Specman experience
-Strong debugging skills
-Experience writing testbenches, test plans, test generation, etc. -Good skills in VHDL or Verilog
-Strong debugging skills
-Experience writing testbenches, test plans, test generation, etc. -Good skills in VHDL or Verilog
Additional Skills (nice to have):
-Good Perl, TCL, Shell scripting experience for ASIC Verification purposes
-Good programming skills in C Verification experience in chip level memory sub-systems like cache controller, memory controller or similar DDR memory
-Excellent written and oral communication skills
-Good programming skills in C Verification experience in chip level memory sub-systems like cache controller, memory controller or similar DDR memory
-Excellent written and oral communication skills
2. Position: VLSI Physical Design Engineer
PD Tasks:
-Integration/DIX checks/IR analysis
-BE checks + DRC/LVS clean up
-Physical Design closure + STA for PHY macro
-Physical Design closure in Cadence EDI flow
-BE checks + DRC/LVS clean up
-Physical Design closure + STA for PHY macro
-Physical Design closure in Cadence EDI flow
3. Position: VLSI DFT Engineer
DFT Tasks:
-PBIST TDL generation and QC
-ATPG / TFT TDL generation and QC – Cadence
-ATPG / TFT TDL generation and QC – Cadence
Contact Details
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HR Department
Indiajobsdb.com
hrd@indiajobsdb.com
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